This invention relates to methods for testing semiconductor devices and more specifically to methods for testing integrated circuits.
During manufacturing, a set of integrated circuits is formed in a semiconductor wafer. After the integrated circuits are formed in the wafer, each circuit within the wafer is tested. Thereafter, the wafer is cut into individual integrated circuits. The circuits which have failed the test are discarded, while the circuits which have passed the test are placed in packages, e.g. dual in-line packages, chip carrier packages, etc. The packaged integrated circuits are then subjected to a final electrical test.
Unfortunately, the results of tests at the wafer level do not always accurately predict how circuits will function at final test. One reason for this is the difference in the dielectric constant of air and mold resin. During wafer test, the top surfaces of the wafers are exposed to air but during final testing, the integrated circuits are assembled into packages, for example, molded plastic packages. Because of this difference in test conditions, the capacitive coupling between two adjacent aluminum, polysilicon or other electrical connection lines in the integrated circuit is different during wafer sort and final test. This difference in capacitive coupling can affect the electrical performance of the integrated circuit.